AMD AMD5K86 - Page 244

18524B/0- Mar1996
Signal Descriptions
AMD~
AMD5t!J6 Processor Technical Reference Manual
the Halt state, the processor transitions to the Stop Grant
state; it then returns to the Halt state when STPCLK is
negated. No processor registers are saved before entering the
Halt state because the processor returns to the next unexe-
cuted instruction in program order when it returns to its prior
operating mode. Within the Halt state, the processor disables
the majority of its internal clock distribution and (if STPCLK
is asserted) the internal pullup resistor on STPCLK. However,
its phase-lock loop still runs, its key internal logic is still
clocked, most of its inputs and outputs retain their last state
(except D63-DO and DP7-DPO, which are floated), and it still
responds to input signals.
The assertion of STPCLK causes the processor to enter the
Stop Grant state. The processor can enter the Stop Grant state
from the normal operating modes (Real, Protected or Virtual-
8086), SMM, or the Halt state. When STPCLK is negated, the
processor leaves the Stop Grant state and returns to the mode
from which it entered. If the Stop Grant state was entered from
the Halt state, negation of STPCLK returns the processor to
the Halt state. Otherwise, negation of STPcLK or assertion of
RESET returns the processor to a normal operating mode
(Real, Protected or Virtual-8086) or SMM. If INIT is asserted in
the Stop Grant state, the signal is latched and acted upon after
STPCLK is negated. No processor registers are saved before
entering the Stop Grant state because the processor returns to
the next unexecuted instruction in program order when it
returns to its prior operating mode. Within the Stop Grant
state (as in the Halt state) the processor disables the majority
of its internal clock distribution and (if STPCLK is asserted)
the internal pullup resistor on STPCLK. However, its phase-
lock loop still runs, its key internal logic is still clocked, most
of its inputs and outputs retain their last state (except D63-DO
and DP7-DPO, which are floated), and it still responds to input
signals.
An inquire cycle driven while the processor is in the Stop
Grant state or the Halt state causes the processor to transition
to the Stop Grant Inquire state. As for inquire cycles driven
from any other state, system logic must assert AHOLD, BUFF,
or HOLD to obtain the address bus before driving EAITS, INV,
and the inquire address. The processor responds normally by
driving llITM and/or HIT and performing any necessary cache-
state transition. If llITM is asserted, the processor drives a nor-
5-125