AMD AMD5K86 - FIGURE 5-2. Single-Transfer Memory Read and Write

18524B/O-Marl996
Bus Cycle Timing
AMD~
AMD5,136 Processor Technical Reference Manual
BRDY, the processor latches the physical address and cycle
definition of the failed bus cycle in its 64-bit machine-check
address register (MCAR) and its 64-bit machine-check type
register (MCTR). For details on such parity errors, see the
descriptions of PCHK and PEN on pages 5-102 and 5-103.
While Figure 5-2 shows BRDY returned in the next clock after
ADS, most DRAM-based systems add wait states (idle clocks)
between ADS and BRDY, as described in Section 5.3.4 on page
5-140.
5-14J