AMD AMD5K86 - Bus Interface

AMD~
185246/0- Mar1996 AMD5K!J6 Processor Technical Reference Manual
A.2 Bus Interface
A.2.1
A.2.2
Bus Interface
Updates to Descriptor Accessed and T55 Busy Bits
For updates to the Accessed bit in the data and code segment
descriptors, the behavior of the AMD5
K
86 processor is differ-
ent than the Pentium processor. In the aligned case, the
AMD5
K
86 processor performs two 4-byte unlocked reads to
read in the descriptor. If the Accessed bit needs to be set, a 4-
byte locked read and a 4-byte locked write will follow. The
Pentium processor performs an 8-byte unlocked read to get the
descriptor. If the Accessed bit needs to be set, an 8-byte locked
read and a i-byte locked write will follow.
For the misaligned case, the AMD5
K
86 processor performs four
unlocked reads to get the descriptor. If the Accessed bit needs
to be set, two locked reads and two locked writes will follow.
The Pentium processor performs two unlocked reads to get the
descriptor. If the Accessed bit needs to be set, two locked
reads will be followed by one i-byte locked write.
For updates to the Busy bit in the TSS descriptor, the
AMD5
K
86 processor behaves in the manner described for
updates to the Accessed bit. The Pentium processor does not
perform the unlocked read to get the descriptor.
Locked and Unlocked CMPXCHG8B Operation
On a locked and misaligned-not on a dword boundary-
CMPXCHG8B operation, the AMD5
K
86 processor performs two
split reads followed by two split writes, all under lock, for a
total of eight cycles. The Pentium processor combines the split
reads and split writes, for a total of four cycles.
On a locked and aligned CMPXCHG8B operation, the
AMD5
K
86 processor performs two reads followed by two
writes, for a total of four cycles. The Pentium processor com-
bines one read and one write, for a total of two cycles.
On an unlocked and non-cacheable CMPXCHG8B operation,
the misaligned and aligned CMPXCHG8B operations are the
A-S