AMD AMD5K86 - DP7-DP0 (Data Parity)

18524B/O-Mar1996
Signal Descriptions
AMD~
AMD5t!J6 Processor Technical Reference Manual
TABLE 5-10. Relation Between 063-00, BE7-BEo, and OP7-0PO
Byte On Data Bus Byte Enable Output Data Parity Bits
D63-D56 BID DP7
D55-D48
BE6
DP6
D47-D40
BE5 DP5
D39-D32
BE4 DP4
D3i-D24 BE3" DP3
D23-D16 BE2 DP2
D15-D8
BEl
DPi
D7-DO
BEU
DPO
During burst reads the processor drives BE7-BEU to identify
only the byte address of the next desired operand. The byte
indication does not change throughout the burst; it continues
to be driven on BE7-~ during all four transfers. The memory
subsystem must ignore BE7-BEU during the second, third, and
fourth transfers of a burst and return all eight bytes corre-
sponding to the eight-byte address on A31-A3. Furthermore,
the memory subsystem must determine the successive
addresses, depending on the starting address that the proces-
sor drives on A31-A3, as described in Table 5-4 on page 5-22.
During writebacks the processor drives all bits of BE7-BEU
Low to indicate that all eight bytes on D63-DO are valid. Write-
backs are addressed by A31-A3, but they are always aligned to
32-byte boundaries so that A4-A3 are always O.
If memory reads, memory writes, or I/O reads are misaligned,
the Pentium processor transfers the highest-addressed portion
followed by the lowest-addressed portion. The AMD5
K
86 pro-
cessor runs such cycles in the opposite order from the Pentium
processor. I/O writes, however, are performed in the same
order on both processors.
5-57