AMD AMD5K86 - Noise Reduction

AMD~
AMDSfIJ6 Processor Technical Reference Manual 18524B/O-Mar1996
&.6 Clock Design
During RESET, the CLK input to the processor should be
grounded until Vee has reached its normal operating level and
PWRGOOD is asserted. Figure 6-7 shows this timing. After Vee
. and CLK reach specification, RESET must be asserted for a
minimum of 1 ms to allow the digital phase-lock loop to syn-
chronize .
...::::...-Vcc __ ~ \
vee at Operating Voltage
PWRGOOD
I
RESET must be asserted
1 ms +-- for at least 1 msafterV
cc
and QK are stable.
--......;
RESET
elK
FIGURE 6-7. Vee and elK
6-40
System Design