AMD AMD5K86 - FIGURE 5-13. BOFF-Initiated Inquire Hit to Modified Line

18524B/O-Mar1996
BOFF-Initiated
Inquire Hit to
Modified Line
Bus Cycle Timing
AMD~
AMD5J!36 Processor Technical Reference Manual
Figure 5-13 shows a burst read interrupted by the assertion of
BUFF for the purpose of an inquire cycle. One clock after sam-
pling BUFF asserted, the processor aborts the burst read and
floats its bus. Two clocks after asserting BUFF, system logic
initiates the inquire cycle by asserting EAUS and INV, and
driving the inquire address on A31-A5. The processor asserts
both HIT and HI'TM two clocks after EAUS, thus indicating
that the inquire hit a modified cache line. The writeback can-
not occur while BUFF is asserted, however, because the proces-
sor has floated its data and control outputs.
After BUFF is negated, the processor writes back the modified
cache line, holding HI'TM asserted until one clock after the last
BRDY of the writeback. Because INV was asserted with EAUS,
the cache line is invalidated after its writeback. Then, the pro-
cessor restarts-from the beginning-the aborted burst read.
For a BUFF inquire cycle to be recognized, BUFF must have
been asserted continuously for two clocks at the time EAUS is
asserted. AHOLD and BUFF can be asserted in conjunction
with each other without interfering with EAUS recognition, as
long as the sampling criteria for at least one of the signals
(AHOLD or BUFF) is met.
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