AMD AMD5K86 - Cache Organization and Management

AMD~
18524BjO- Mar1996
AMD5#6 Processor Technical Reference Manual
2.3 Cache Organization and Management
The performance of the execution pipeline is enhanced by the
processor's on-chip, 16-Kbyte instruction cache and 8-Kbyte
data cache. Both caches are linearly addressed and each has
two associated tag directories, one for linear tags and one for
physical tags.
Linearly addressed caches avoid linear-to-physical address
translation through the TLB and can be faster than physically
addressed caches. Cache accesses in the AMD5
K
86 processor
take one clock. The physical tags are only accessed during
cache misses and snoops. By comparison, accesses in the Pen-
tium processor's physically tagged caches take one or two
clocks, depending on the type of operand being accessed (oper-
ands used in address calculations for the next cache access
take two clocks). Since most x86 instructions access memory,
they benefit greatly by being cached, and the faster cache-
access time on the AMD5
K
86 processor is a performance
advantage.
The enabling and operating modes for the caches are software
controlled by the CD and NW bits of CRO. When disabled, both
caches are locked. They are accessed in all operating modes,
and the processor can still hit in a cache that has not been
invalidated, even if software has turned the caches off. These
mechanisms work the same on both the AMD5
K
86 and Pentium
processors.
Any area of memory may be cached. However, the processor
prevents caching of locked operations and TLB reads, the oper-
ating system can prevent caching of certain pages by setting
the PCD bit in page-directory and/or page-table entries, and
system logic can prevent caching of certain bus cycles by
negating the KEN input signal on the first BRDY.
The processor implements a requested-word-first protocol for
line fills in both caches. Upon receiving the first 8-byte quad-
word, execution continues while the remainder of the line is
loaded into the cache. Both caches, however, are blocking-a
read hit or miss after a read miss waits until the prior miss fills
the cache. Since read misses are rare, relative to read hits,
cache blocking has little effect on overall performance.
Cache Organization and Management
2-lJ