AMD AMD5K86 - SCYC (Split Cycle)

AMD~
AMDSflJ6 Processor Technical Reference Manual 18524BjO-Marl996
5-114
address limit required in Real mode. (The physical address
OOOF _FFFOh is sometimes written in the selector:offset format
as FOOO:FFFO.) This reset address behavior of the x86 architec-
ture is due to the special way in which segment translation is
performed on reset. Normally, a Real-mode 16-bit segment
selector is shifted left 4 bits (one hex digit) to form the seg-
ment base, and then added to the 16-bit offset. Thus,
FOOO:FFFO in the selector:offset format becomes a segment base
of FOOOOh added to an offset of FFFOh, yielding the physical
address OOOF _FFFOh. When RESET is asserted, however, the
left shift is not done and the high 16 address bits are all set to
1, yielding the physical address FFFF _FFFOh. Thereafter,
address translation only begins to work in the normal Real-
mode manner when the first far jump is executed. This jump
loads the code segment register with a 16-bit segment selector.
This code segment load causes the address translation mecha-
nism to begin working normally. The system logic address
decoder must make this behavior transparent to software by
aliasing the physical address FFFF _FFFOh to the physical
address OOOF _FFFOh.
The processor recognizes AHOLD, BUFF, and HOLD while
RESET is asserted, but these signals will not intervene in the
initialization process except that they will prevent the first
code fetch (jump to BIOS) after the registers are initialized.
While RESET is asserted, the processor recognizes or drives
only BF, FLOSH, FRCMC, the hold signals (AHOLD, BUFF,
HOLD, and HLDA), INIT, and R/S.
Unlike the Pentium processor, the AMDS
K
86 processor does
not recognize RESET in the Hardware Debug Tool (HDT)
mode. System hardware or software must exit the HDT (by
driving R/S High) before asserting RESET.
Bus Interface