AMD AMD5K86 - Page 232

1 8524BjO-Marl 996
Signal Descriptions
AMD~
AMD5/36 Processor Technical Reference Manual
TABLE 5-16. Outputs at RESET
Output
RESET State
ADS 1
A31-A3 Floating
APCHK
1
:BEl-BED FFh
BREQ
1
BRDY 1
BRDYC
1
CACHE
1
D/C 0
D63-DO
Floating
DP7-DPO OOh
FERR 1
HIT 1
IIITl\I 1
HLDA
0
mcK
1
M/ID 0
PCD 0
PCHK
1
PRDY
0
PWT 0
W!R
0
Unlike INIT, RESET reinitializes the processor's entire state.
In particular, RESET differs by reinitializing the contents of
the caches, floating-point registers, control registers, and
model-specific registers, as well as all other states that are
reinitialized by INIT.
:AZOM: should not be asserted during RESET. The operating
system alone is responsible for controlling the state of :AZOM:
by writing to an external register provided for this purpose.
(See the description of:AZOM: on page 5-19.)
Because the processor boots in Real mode, the memory address
decoder must alias the physical address FFFF _FFFOh to the
physical address OOOF _FFFOh, which lies within the l-Mbyte
5-11J