AMD AMD5K86 - Exceptions; Limit Faults on an Invalid Instruction; Task Switch

AMD~
AMD5~6 Processor Technical Reference Manual
18524B/O-Marl996
A.&
A.6.1
A.6.2
A-14
Exceptions
Limit Faults on an Invalid Instruction
When executing an instruction that crosses a limit boundary
and the instruction is interpreted as invalid, the AMDS
K
86 pro-
cessor prioritizes the invalid opcode fault. The Pentium and
486 processors prioritize the limit violation fault.
Task Switch
On a task switch, the AMDS
K
86 processor sets the busy bit of
the incoming task after storing the outgoing TSS according to
486 and Pentium processor documentation. The Pentium pro-
cessor sets the busy bit before trying to store the outgoing TSS.
If a fault occurs while trying to store the TSS, the Pentium pro-
cessor clears the busy bit. The end result of the instruction is
the same on both processors.