AMD AMD5K86 - Debug; Simultaneous Debug Trap and Debug Fault

AMD~
1 B524B/O-Mar1996 AMD5t!J6 Processor Technical Reference Manual
A.7 Debug
A.7.l
A.7.2
A.7.3
Debug
Proprietary Branch Trace Messages
Branch trace messages are different. The AMD5
K
86 processor
uses the same BE pattern for the special bus cycles as the Pen-
tium processor, but the format of decoding information is dif-
ferent.
Multiple Debug Breakpoint Matches
Multiple debug breakpoint matches do not set multiple B bits
in DR6 on the AMD5
K
86 processor.
Simultaneous Debug Trap and Debug Fault
If a debug trap associated with the completion of an instruc-
tion (single-step trap or load/store breakpoint) occurs at the
same time as a debug fault (instruction breakpoint) on the next
instruction, the Pentium processor merges the two conditions
into a single call to the debug handler, setting both B bits in
the debug status register. The AMD5
K
86 processor processes
the two conditions serially, setting the appropriate B bits for
each invocation of the handler.
A-IS