AMD AMD5K86 - TABLE 5-2. Conditions for Driving and Sampling Signals

AMD~
AMD5~6 Processor Technical Reference Manual
1 8524B/O-Marl 996
TABLE 5-1. Summary of Signal Characteristics (continued)
Signal Type
Sampled (Input) or
Internal
Floated
3
Asserted (Output)2
Resistor
W/R 0
From AUS until last expected BRDY of the
:BUFF +1 or
bus cycle. HLDA
WBIWT I
First :BRDY or NA of bus cycle, whichever
comes first.
Notes:
I.
2.
3.
5.1.2
5-8
Can be driven asynchronously or synchronously.
The term clock means bus clock (CLK). "+n" means n CLKs later.
"+n" means n CLKs after the named signal is sampled active. All outputs and bidirectionals are floated during the float test (FITfSR
at RESET).
Conditions for Driving and Sampling Signals
Table 5-2 shows the processor states, signal states, and bus
cycles during which the processor can drive or sample each sig-
nal. The table indicates when signals can be driven or sampled
so that their state has some practical (meaningful) effect on
the state of the processor or on the bus cycle being driven or
sampled. In Table 5-2, shading indicates signals that are mean-
ingfully driven or sampled. Signals that are not shaded are not
driven or sampled or are not meaningful. For details on how
each signal behaves, see Section 5.2 starting on page 5-18.
Bus Interface