AMD AMD5K86 - Locked Cycles

18524B/O- Mar1996
HOLD-Initiated
Inquire Hit to
Modified Line
AMD~
AMD51J6 Processor Technical Reference Manual
Figure 5-15 shows an example similar to the one in Figure 5-14,
except that the inquire cycle hits a modified line (both HIT and
IIITNI asserted two clocks after EXDS). System logic negates
HOLD in the clock after EADS, and two clocks later (one clock
after HIT and IIITNI transition) the processor negates HLDA.
As
early as one clock after negating HLDA, the processor
asserts ADS to drive the writeback, after which the processor
invalidates its copy of the line.
MI:~~~~~
BEl-BED
L'ACRE
o/C
063-00
HLDA
HOLD
INV
M/fO
t
I
I
,
i
I \f-J
I
: Read
I
~
I
\
I
\
I
fIl
I
I
I
: Inquire
RGURE 5-15. HOLD-Initiated Inquire Hit to Modified Line
Bus Cycle Timing
X
\
\
iii I
I
: Writeback
5-169