AMD AMD5K86 - FIGURE 5-23. Cache-Invalidation Cycle (INVD Instruction)

AMD~
AMD5~6 Processor Technical Reference Manual
18524B/O-Mar1996
FIlJSH-Acknowledge
Cycle
Figure 5-22 shows the FLUSH-acknowledge special bus cycle,
which the processor drives in response to system logic's asser-
tion of FLUSH. This example shows the processor completing
other unrelated bus cycles following the assertion of FLU SH.
These bus cycles are caused by the execution of instructions
earlier in the pipeline, which are completing execution before
the processor recognizes FLUSH on the next instruction-retire-
ment boundary.
ClK
A31-A3
ID-BEO
tAmE
o/C
063-00
FIlJ5II
KEN
IOCR
M/IU
W/R
ClK
FLUSH causes the processor to write back all modified lines in
its data cache. Only one such writeback is shown in this exam-
ple.
After all writebacks complete, the processor invalidates
all lines in both of its caches. Then, the processor generates the
FLUSH-acknowledge special bus cycle (BE7-BEU = EFh) to
indicate that the writebacks and invalidation have completed.
System logic must respond by asserting BRDY.
dx'-'!r-->--+-+-+-+--+;xv-+-: -+--+-+-+--+-
~~,L:~+-~~:~r~i~+-+-~
~~!~-+-+-+-+~:K~I-+-+-+-+-+-
~
Ti i~i ill
J-JW-J-JJ-
1x
ri
-r--t-1'-r--hI'
1J...-t-i --r-+---t-..-;-
\ .
•••
I i
~~,~~-+-~~rl-+-r+-
I
: Flush Asserted
Jr+-I -t--'--1--!--+--+-+
i
tWm91-
+-+' --+- ........ ~t-! -+-t-+
Jr-:r-: +-t--+-+-+-t-+
: i : 'ii'! i
L.flILflf1.MJlJ
I
I
Writeback
.
: ivi:,:
JJ! i
••• [\,-+-1 -+--+-+---1-+
! id>! ! i !
~!
~!
u-u-u-uwJ
FIGURE 5-22. FlUSH-Acknowledge Cycle
5-184
Bus Interface