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AMD AMD5K86 - FIGURE 7-1. Hardware Configuration Register (HWCR)

AMD AMD5K86
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AMD~
AMD5~6
Processor
Technical
Reference
Manual
18524B/O-Mar1996
7-2
• Test Access Port (TAP) Boundary-Scan
Testing-The
JTAG
test
access
functions
defined
by
the
IEEE
Standard
Test
Access Port
and
Boundary--Scan Architecture (IEEE 1149.1-
1990)
specification.
• Hardware Debug Tool
(HDT)-The
hardware
debug
tool
(HDT),
sometimes
referred
to
as
the
debug
port
or
Probe
mode,
is
a
collection
of
signals,
registers,
and
processor
microcode
that
is
enabled
when
external
debug
logic
drives
RIS Low
or
loads
the
AMD5
K
86
processor's
Test
Access
Port
(TAP)
instruction
register
with
the
USEHDT
instruction.
The
test-related
signals
and
their
descriptions
include
the
fol-
lowing:
•
FLUSH-Page
5-67
•
FRCMC-Page
5-70
•
!ERR
-
Page
5-80
•
INIT -
Page
5-82
•
PRDY-Page
5-104
•
RIS-Page
5-108
•
RESET-Page
5-110
•
TCK-Page
5-128
•
TDI-Page
5-129
•
TDO-Page
5-130
•
TMS-Page
5-131
•
TRST
-
Page
5-132
The
sections
that
follow
provide
details
on
each
of
the
test
and
debug
features.
Test
and
Debug

Table of Contents

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