AMD AMD5K86 - 4-Mbyte Pages

AMD~
18524B/O-Marl996 AMD5/l6 Processor Technical Reference Manual
3.1.2 4-Mbyte Pages
r
I
CR3
I
I
31
Page Directory
Offset
The TLBs in the 486 and 386 processors support only 4-Kbyte
pages. However, large data structures such as a video frame
buffer or non-paged operating system code can consume many
pages and easily overrun the TLB. The AMD5
K
86 processor
accommodates large data structures by allowing the operating
system to specify 4-Mbyte pages as well as 4-Kbyte pages, and
by implementing a four-entry, fully-associative 4-Mbyte TLB
which is separate from the 128-entry, 4-Kbyte TLB. From a
given page directory, the processor can access both 4-Kbyte
pages and 4-Mbyte pages, and the page sizes can be intermixed
within a page directory. When the Page Size Extension (PSE)
bit in CR4 is set, the processor translates linear addresses
using either the 4-Kbyte TLB or the 4-Mbyte TLB, depending
on the state of the page size (PS) bit in the page-directory
entry. Figures 3-2 and 3-3 show how 4-Kbyte and 4-Mbyte page
translation work.
4-Kbyte
Page
Directory
PDE
22 21
t--
r
Page Table
Offset
4-Kbyte
Page
Table
PTE
Linear Address
1---
r--+
12 11
Page
Offset
4-Kbyte
Page
Byte
0
FIGURE 3-2. 4-Kbyte Paging Mechanism
Control Register 4 (CR4) Extensions
J-5