AMD AMD5K86 - FRCMC (Functional-Redundancy Check Master;Checker)

18524B/O-Marl996
Signal Descriptions
AMD~
AMD5J!16 Processor Technical Reference Manual
When BUFF is subsequently negated, the writeback is
restarted and the FLUSH operation continues from where it
left off. Any writebacks that completed before BUFF was
asserted are not affected by BUFF's intervention.
If FLUSH is asserted while AHOLD, BUFF, or HLDA is
asserted, the outcome of the flush depends on whether the
flush causes writebacks of modified lines. If no writebacks are
needed, the processor invalidates all lines but does not per-
form the FLUSH-acknowledge cycle until the processor gets
control of the bus again. If a writeback is needed, the processor
stops at that write back, without having invalidated any lines,
waits until control of the bus is returned to the processor, then
completes the FLUSH operation. If FLUSH is asserted during
the Stop Grant state, the signal is held pending until after the
processor exits the Stop Grant state, at which point it is acted
upon.
No other interrupt or exception will intervene in a flush opera-
tion because such interrupts are not recognized until after the
FLUSH-Acknowledge special bus cycle, which occurs at the
end of all writebacks and invalidations. The processor latches
the assertion of any edge-triggered interrupt (FLUSH, SNIT,
INIT, NMI) while FLUSH is asserted and recognizes latched
interrupts in priority order when FLUSH is negated.
The Three-State (float) Test mode, entered if FLUSH is
asserted during RESET, causes the processor to float all of its
output and bidirectional signals. In this isolated state, system
board traces and connections can be tested for integrity and
drive ability. The Float-Test mode can only be exited by assert-
ing RESET again.
On the AMD5
K
86 and Pentium processors, FLOSH is an edge-
triggered interrupt. On the early 486 processors, however, the
signal is a level-sensitive input.
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