AMD AMD5K86 - Page 187

AMD~
AMD5,!J6 Processor Technical Reference Manual 18524B/O-Mar1996
5-68
use the Flush-Acknowledge special bus cycle to initiate such
action.
Entry into SMM may require the assertion of FLUSH. If the
SMM physical memory space overlaps physical main memory
that is cacheable, FLUSH must be asserted with sm (the
FLUSH will be performed first, because it is a higher-priority
interrupt). If this is not done, accesses to the SMM memory
space after entering SMM may hit cached locations in the main
memory space. In addition, if SMM memory is itself cacheable,
the SMM service routine should execute the WBINVD (write-
back and invalidate) instruction when leaving SMM, just prior
to executing the RSM instruction.
The processor performs the FLUSH operation using the same
microcode that executes for the WBINVD (write back and inval-
idate) instruction. The only difference is the special bus cycle
driven upon completion of the operation. A write back and
invalidation operation can be time consuming because all mod-
ified lines in the data cache are written back to memory. If
write backs are not required, the INVD instruction or RESET
can be used to invalidate all contents of the caches.
When FLUSH is recognized at an instruction boundary, the
processor performs the following actions in the order shown:
1. Flush Pipeline-The processor invalidates all instructions
remaining in the pipeline.
2. Writeback and Invalidate- The processor writes back any
modified lines in the data cache, and then (after all write-
backs) simultaneously invalidates all lines in the instruc-
tion and data caches. The invalidations are done by clearing
the valid bits in both the linear and physical tag directories.
3. Acknowledge-After the write back and invalidation com-
pletes, the processor drives a FLUSH-acknowledge special
bus cycle. This cycle is identified by DiC = 0, M!IU = 0, WIR
= 1, BE7-BEU = EFh and A31-A3 = 0. System logic must
return BRDY in response to this cycle.
AHOLD, BUFF, and HOLD are all recognized and behave nor-
mally while FLUSH is asserted, and they will intervene in an
in-progress FLUSH operation. For example, if BUFF is
asserted while a FLUSH operation is writing modified lines
back to memory, an in-progress writeback will be aborted.
Bus Interface