AMD AMD5K86 - AP (Address Parity)

18524BjO-Mar1996
Signal Descriptions
AMDit1
AMD5t116 Processor Technical Reference Manual
BREQ asserted continuously. For a list of signals recognized
while AHOLD is asserted, see Table 5-2 on page 5-9.
The processor may again drive its own cycles with ADS as early
as one clock after system logic negates AHOLD. Before negat-
ing AHOLD, however, system logic may need to arbitrate
among potential contenders for the address bus so as to avoid
deadlock contention for the bus.
Ground-bounce spikes can be avoided by following two rules
with respect to AHOLD:
•
Do not negate AHOLD in the same clock that BRDY is
asserted during a write cycle.
• Do not negate AHOLD in the same clock that ADS is
asserted during a writeback.
These restrictions must be observed because the processor's 32
address drivers turn on almost immediately after AHOLD is
negated. If the processor is driving data withBRDY on the 64-
bit data bus at the same time, the processor then drives 96 bits
simultaneously and ground-bounce spikes can occur.
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