AMD AMD5K86 - Page 149

AMD~
AMD5xB6 Processor Technical Reference Manual 18524B/O-Mar1996
5-JO
When the processor releases control of A31-A3 and AP in
response to AHOLD, the processor still maintains control of
the remaining signals on the bus so that it can (a) finish driving
a bus cycle it may have begun before AHOLD was asserted,
and (b) drive a writeback if an inquire cycle hits a modified
line in the processor's data cache. However, the processor can-
not begin driving a new bus cycle while AHOLD is asserted
because system logic controls the address bus.
System logic drives inquire cycles with the EA1JS, A31-A5, AP
and INV inputs. A typical sequence for an inquire cycle is:
assert AHOLD; two clocks later, assert EA1JS and drive A31-
AS and INV; wait two clocks for the processor to assert HITlVI
and/or HIT. If HITlVI remains negated two clocks after EAIJS is
asserted, the inquire cycle ends. If HITlVI is asserted at that
time, the processor begins driving a four-transfer burst write-
back as early as two clocks after asserting HITlVI.
AHOLD can be negated as early as one clock after EA1JS is
asserted. If system logic holds AHOLD asserted throughout an
inquire cycle and any required writeback, system logic must
latch the inquire cycle address when it asserts EA1JS. This is
required so that, if the inquire cycle hits a modified line
(HITlVI asserted), the address used for the writeback need not
be driven by the processor when the processor asserts ADS for
the writeback. Instead, A31-A5 remains an input-only bus and
system logic must use its latched copy of the inquire cycle
address. By contrast, if system logic always negates AHOLD
before the writeback, the processor drives the writeback
address when it asserts ADS for the writeback, and system
logic need not retain a copy of the inquire cycle address. While
the processor drives the writeback address, it drives only the
beginning address for the 32-byte transfer on A31-A5. System
logic must determine the remaining addresses as shown in
Table 5-4 on page 5-22.
If system logic asserts AHOLD while the processor is driving a
locked cycle, the system must not allow accesses by other bus
masters to lock the same address that the processor is locking.
While AHOLD is asserted (after the completion of any in-
progress bus cycle by the processor), the processor continues
to execute out of its instruction and data caches, if possible. If
the processor can no longer operate out of its caches, it holds
Bus Interface