AMD AMD5K86 - AHOLD (Address Hold)

AMD~
18524B/O-Mar1996 AMD5,!J6 Processor Technical Reference Manual
5.2.5 AHOLD (Address Hold)
Summary
Sampled
Details
Signal Descriptions
Input
System logic can assert AHOLD to obtain control of the bidi-
rectional A31-A3 address bus and AP address parity signal to
drive one or more inquire cycles to the processor.
The processor samples AHOLD in every clock and responds by
floating the bidirectional A31-A3 and AP signals one clock
after AHOLD is asserted.
AHOLD is sampled during memory cycles (including cache
writethroughs and writebacks), 110 cycles, inquire cycles,
locked cycles, writebacks, special bus cycles, and interrupt
acknowledge operations in the normal operating modes (Real,
Protected, and Virtual-8086) and in SMM; in the Shutdown,
Halt, or Stop Grant states; or while RESET, INIT or PRDY is
asserted. AHOLD is sampled but not effective when BUFF or
HLDA is asserted. AHOLD is not sampled during the Stop
Clock state.
The sole function of AHOLD is to support inquire cycles. There
are three methods by which system logic can obtain control of
the address bus to drive an inquire cycle: AHOLD, BUFF, or
HOLD. AHOLD obtains control only of the address bus and
allows another master or system logic to drive only inquire
cycles, whereas BUFF and HOLD obtain control of the full bus
(address and data), allowing another master to drive not only
inquire cycles but also read and write cycles. AHOLD and
HOLD both permit an in-progress bus cycle to complete, but a
writeback can occur while AHOLD is asserted, whereas a pend-
ing writeback during the assertion of BUFF or HOLD occurs
after the BUFF or HOLD is negated.
AHOLD is useful primarily in systems with multiple buses and
multiple bus masters, where operations can occur on the sepa-
rate buses independently and in parallel. This configuration
occurs, for example, if the processor shares a bus only with a
look-through L2 cache, and other caching masters work in par-
allel on another bus that is isolated from the processor by sys-
tem logic. In such designs, system logic may drive separate
AHOLD signals to each bus master in the system. For details
on how AHOLD can be driven in such configurations, see Sec-
tion 6.2.5 on page 6-14.
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