AMD AMD5K86 - Bus Cycle Overview

AMD~
185248/0- Mar1996 AMD5i!J6 Processor Technical Reference Manual
5.3 Bus Cycle Overview
The bus signals described in the previous section combine to
form various types of bus transactions, or bus cycles. This sec-
tion summarizes the general features of the bus cycles: cycle
definition, addressing, alignment, and priorities. Section 5.4
describes the signal timing for specific types of bus cycles.
5.3.1
Cyde Definitions
The processor begins driving a bus cycle when it asserts ADS.
Concurrent with ADS, it drives the set of signals indicated in
Table 5-19, which define the type of bus cycle. For memory
reads, memory writes, burst reads, and burst writes, D/C speci-
fies whether the bus cycle accesses code (instructions) or data.
MIIO specifies whether the cycle accesses memory or an I/O
port. W!R specifies whether the cycle is a read or write. The
assertion of CACHE indicates that the processor is writing or is
prepared to read a burst cycle consisting of four consecutive
transfers on the data bus. However, for a read, system logic
must confirm the burst by asserting KEN, or the bus cycle
becomes a single-transfer read. I/O accesses are always non-
burst cycles.
TABLE 5-19. Bus Cycle Definitions
Signals
Type of Cycle Comments
DiC M/ID WIR CACHE
Single-Transfer Memory
o or 1
1
o or 1
1
-
Read or Write
Single-Transfer I/O Read
1 0 o or 1 1
-
or Write
Burst Memory Read or
o or 1 1 o or 1 0
For reads, system logic must
Write assert KEN with BRDY.
Interrupt Acknowledge
0 0 0
-
Pair of locked cycles.
Several special cycles dis tin-
Special
0 0 1
-
guished by BE7-ImU and
A31-A3. See Table 5-23 on
page 5-181.
Bus Cycle Overview S-U7