AMD AMD5K86 - FIGURE 5-14. HOLD-Initiated Inquire Hit to Shared or Exclusive Line

1 B524B/O-Mar1996
HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Bus Cycle Timing
AMD~
AMD5~6 Processor Technical Reference Manual
Figure 5-14 shows HOLD asserted in the same clock that the
processor begins a read cycle. The processor completes the
read (which is a burst read) and asserts HLDA two clocks after
the last BR1JY of the in-progress cycle. It also floats all output
and bidirectional signals used for memory or I/O accesses at
the same time it asserts HLDA.
In the next clock after sampling HLDA asserted, system logic
initiates an inquire cycle by asserting EXITS and INV and driv-
ing an inquire address on A31-A5. The inquire cycle hits a
shared or exclusive line (HIT asserted and HITlVI negated two
clocks after EXITS) and the processor invalidates the cache
line (not visible on the bus). System logic negates HOLD in the
clock after EXITS, and two clocks later (one clock after HIT
and HITlVI transition) the processor negates HLDA and contin-
ues with its other bus cycles.
If EXITS is asserted in the same clock that HOLD is negated,
the processor recognizes this as a valid inquire cycle and han-
dles it correctly. However, if EXITS is asserted in the clock fol-
lowing the negation of HOLD, the processor does not recognize
this as a valid inquire cycle.
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