AMD AMD5K86 - Store Buffer

AMD5J136 Processor Technical Reference Manual
18524BjO-Mar1996
Prefetch Cache
Store Buffer
2-24
access. As shown in Table 2-4, the line-fill buffer for the
instruction cache is snooped internally during read or write
misses in the data cache, but it is not snooped during inquire
cycles. The line-fill buffer for the data cache, unlike the
instruction-cache buffer, is never snooped and for this reason
does not appear in Table 2-4.
The processor pre fetches instructions during fetch-stage
misses in the instruction cache, as described in Section 2.1 on
page 2-3. When a miss occurs, the processor initiates a 32-byte
access for a 16·byte line fill and additional sequentially
addressed bytes to fill the prefetch cache. During non-cache-
able accesses, the fetch logic fetches directly from the pre fetch
cache.
As shown in Table 2-4 on page 2-22, the pre fetch cache is
snooped internally during read or write misses in the data
cache and during inquire cycles.
The Pentium processor implements a write buffer in which
real-state data writes can be buffered, waiting for access to the
bus, and in which certain types of cacheable read cycles on the
bus are promoted ahead of certain types of write cycles when
the EWBE signal is asserted. The AMDS
K
86 processor has no
such real-state write buffer between its data cache and the bus,
although it does implement a speculative-state, 4-entry, 4-byte-
wide store buffer between the two load/store execution units
and the data cache.
The store buffer can contain both speculative- and real-state
data. Each entry in the store buffer is in speculative state until
the associated ROP is retired, after which the data is trans-
ferred to the data cache and/or memory, both of which repre-
sent the real (non-speculative) state of data. A store occurs at
the retirement stage of the pipeline, when the processor writes
an entry from the store buffer to the data cache and/or mem-
ory. For non-cache able stores, the processor writes directly
from the store buffer to the bus interface, at which point the
store becomes real-state.
As shown in Table 2-4 on page 2-22, the store buffer is not
snooped during inquire cycles. When external logic drives an
inquire cycle, the processor's response depends only on the
contents of the data cache at that time (that is, only on its real
state). Subsequent stores to that line-be they in the store
Internal Architecture