AMD AMD5K86 - Prefetch and Predecode

AMD~
AMD5IJ6 Processor Technical Reference Manual
1 8524B/O-Marl 996
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Prefetch & Predecode
I-~
Instruction
Cache
.-
Branch Prediction
l-
f----
Linear Tags
(0
•
Fetch
I
Byte
Queue
•
I
Fast
M Fast
c:e I
I
Fast
c:e I
I
Fast
c:e I
Path Code Path
Path Path
J
+!1
+ + +
++ ++
+++
R.S.
R.5. R.5.
R.5.
L
R.S.
J
ALU
ALU FPU Branch
j
J_
_,_ -.i
0)
J
Load J
~
Load J
J
Store
Store
J
Execute
J
• •
4 Ports
J
J
I
---------------y
I
------------------
I
I
5 Ports
r------
L ___
.t
I
I
I
Reorder Buffer
I
Store
J
8 Ports
I
(ROB)
.------
Buffer
I
I
]
0
Result
4 Ports
I
t
I
I
I
Register File
I
Data
~
8 Ports
I
(x86 GPRs, FPRs)
J
Cache
J
,------.
Linear Tags
t
}"
--------------.
Memory Management Unit
(TLBs and Physical Tags)
I
J
t
•
-'-
Fastpath
Hardware ROPs
Bus Interface Unit
M Code Microcode ROPs
R.S.
Reservation Station
t 64
Port 41 bits
J 32
Address
..
-- -.
_ Data
FIGURE 2-1. Internal Architecture, with Pipeline Stage
2-2 Internal Architecture