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AMD AMD5K86 - CLK (Bus Clock)

AMD AMD5K86
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AMD~
AMD5~6
Processor
Technical
Reference
Manual
18524B/O-Mar1996
CACHE
is
not
asserted
for
the
following
types
of
memory
reads
(MfID
= 1):
•
Locked
reads
(that
is,
while
IDCK
is
asserted)
• TLB
reads
•
Any
read
with
PCD
asserted
(PCD
is
a
factor
in
determining
the
state
of
CACHE)
TABLE
5-9.
MESI-State
Transitions
for
Reads
Result
of
Cache
Lookup
Signal
or
Event
Read
Hit
Read
Miss
shared
exclusive
modified
CACHE,
PCDl
1
-
0 0 0
- - -
KEN
-
1 0 0 0
- - -
PWT
- -
1
-
0
- - -
WB/WT
- - -
0 1
- - -
Cache
Line
Fill
(32
bytes)
no no
yes
yes
yes
no no
no
State
After
Read
2
- -
shared shared exclusive shared exclusive modified
Notes:
-
Don't
care
or
not
applicable.
I.
2.
5-52
The
PCD
bit
is
one
determinant
of
the
state
of
rACRE.
Transition
occurs
after
any
line
fill.
Lines
in
"shared"
MESI
state
are
said
to
be
in
"writethraugh"
state.
Those
in
"exclusive"
or
"mod-
ified"
MESI
states
are
said
to
be
in
"writeback"
state.
On
the
486
processor,
by
comparison,
the
CACHE
output
does
not
exist,
but
the
BLAST
output
(in
conjunction
with
KEN)
serves
to
determine
cache
ability.
Although
bursts
are
typically
four
32-bit
transfers
on
the
486
processor,
they
can
be
longer
with
narrower-width
memories.
Bus
Interface

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