AMD AMD5K86 - Clock Design

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Power and Ground Design
AMD~
AMD51J6 Processor Technical Reference Manual
immediately after AHOLD is negated. If the processor is also
driving data with BRDY on the data bus at the same time, the
processor then drives 96 bits simultaneously and ground-
bounce spikes can occur. Such ground-bounce spikes can be
avoided by following these two rules with respect to AHOLD:
•
Do not negate AHOLD in the same clock that BRDY is
asserted during a write cycle.
• Do not negate AHOLD in the same clock that ADS is
asserted during a writeback.
In addition to the above restrictions on driving AHOLD, the
following general design recommendations apply to power con-
nections between the processor and the system board:
• Connect all Vee pins to a V cc plane on your system board.
• Connect all V ss pins to a GND plane on your system board.
• Do not drive address and data buses into large capacitive
loads at high frequencies. This can cause transient power
surges.
• Decouple capacitance near the processor.
• Use low-inductance capacitors and circuit paths, and type
X7R or better dielectric.
• Use capacitors specifically designed for PGA packages.
• Tie unused inputs High or Low.
• Leave no-connect (NC) pins unconnected.
• Connect active-Low inputs to Vee through a 20-kQ pullup
resistor. This keeps the inputs in a known state while allow-
ing them to be driven during tests.
• Connect active-High inputs to GND through a pulldown
resistor.
• Keep trace lengths to a minimum.
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