AMD AMD5K86 - SMM Compatibility with Pentium Processor

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AMD5J36 Processor Technical Reference Manual 1 8524B/O-Marl996
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tion 6.3.6. The SMM service routine should test bit 1 of the 110
trap dword to determine the validity of the 110 instruction
before writing the 110 trap restart slot. If the 110 instruction
was valid, the SMM service routine can safely rewrite the 110
trap restart slot with the value OOFFh, which causes the proces-
sor to re-execute the trapped I/O instruction when the RSM
instruction is executed. If the 110 instruction was invalid, writ-
ing the 110 trap restart slot has undefined results. If sequential
SMI interrupts occur, the second entry into SMM will never
have bit 1 of the I/O trap dword set, and the second SMM ser-
vice routine should not rewrite the 110 trap restart slot.
The pseudo-code for implementing 110 Trap Restart in BIOS is
as follows:
begin
{
if liD instruction needs to be restarted then
{
if valid liD instruction (test offset FFA4) then
set liD restart slot (offset FFOO) to OOFFh
end
During a simultaneous s:MI IIO-instruction trap and debug
breakpoint trap, the AMD5
K
86 processor first responds to the
SMI and postpones writing the exception-related information
to the stack until after the return from SMM via the RSM
instruction. If debug registers DR3-DRO are used in SMM, they
must be saved and restored by the SMM software. The proces-
sor automatically saves and restores DR7-DR6. If the 110 trap
restart slot in the SMM state-save area is written with the
value OOFFh when the RSM instruction is executed, the debug
trap does not occur until after the 110 instruction is re-exe-
cuted.
Exceptions and Interrupts in SMM
When SMM is entered, the processor disables both INTR and
NMI interrupts. On both the AMD5
K
86 and Pentium proces-
sors,
INTR interrupts are disabled by clearing the IF flag in
EFLAGS. But the mechanism by which NMI interrupts are dis-
abled and subsequently recognized differs between the
AMD5
K
86 and Pentium processors.
System Design