AMD AMD5K86 - Snoop Writeback Buffer

18524B/O-Mar1996
Replacement and
Invalidation
Writeback Buffer
AMD~
AMD5~6 Processor Technical Reference Manual
buffer, load/store execution units, reservation stations, decode
unit, or prefetch cache-are not relevant to an inquire cycle or
internal snoop. Such stores are speculative and might never
occur, due to a branch misprediction, an interrupt, or other
intervening event.
As a buffered store leaves the store buffer to update the data
cache and/or memory, the processor checks the location's
MESI state in the physical tags and observes the MESI update
rules for that state. For example, if a buffered store were going
to hit an exclusive line in the data cache when first placed in
the store buffer, but the line's MESI state was changed from
exclusive to shared by a subsequent inquire cycle while the
store waited in the store buffer, the store would see a shared
state on being transferred to the data cache, and it would
become a writethrough, going externally to main memory at the
same time that it updates the data cache.
The processor has a l-entry, 32-byte-wide writeback (copy-
back) buffer in the bus interface unit for replacements and
invalidations. The buffer is used for writebacks of modified
data in the data cache due to one of the following:
• Cache-line replacement during data-cache read miss
• WBINVD instruction
• FLUSH signal
During cache-line replacements, the memory read cycle for the
new cache line is initiated on the bus before the contents of the
modified line to be replaced are copied into the writeback
buffer. When the cache-line fill is completed, the contents of
the writeback buffer are written to memory.
Writethroughs from the data cache do not go through a buffer.
These transfers are between 1 and 8 bytes in length and they
go directly onto the bus from the store buffer.
As shown in Table 2-4 on page 2-22, the writeback buffer is
snooped internally during instruction-cache read misses and
during inquire cycles.
Cache Organization and Management
2-25