AMD AMD5K86 - WB;WT (Writeback or Writethrough)

AMD~
AMD5,!J6 Processor Technical Reference Manual 18524B/O-Mar1996
5.2.56
Summary
Sampled
Details
5-U4
WBjWT (Writeback or Writethrough)
Input
WBIWT,together with PWT, specifies the data-cache MESI
state of cacheable read misses and write hits.
The processor samples WBIWT in the same clock as the first
BRDY of a bus cycle or NA, whichever comes first.
WBIWT is sampled during memory reads and writes, including
writebacks, in the normal operating modes (Real, Protected,
and Virtual-8086) and SMM, and when PRDY is asserted. WBI
WT is not sampled during 110 cycles, locked cycles, special bus
cycles, or interrupt acknowledge operations; or during the
Shutdown, Halt, Stop Grant, or Stop Clock states; or while
BUFF, HLDA, RESET, or INIT is asserted. While AHOLD is
asserted, WBIWT is sampled only to complete a bus cycle
begun before the assertion of AHOLD.
Lines in the shared MESI state are said to be in the
writethrough state. Those in the exclusive or modified MESI
state are said to be in the writeback state. When a write access
either misses the data cache or hits a shared line in the data
cache, the processor drives a 1-to-8-byte write cycle (called a
writethrough) on the bus. When an inquire cycle, internal
snoop, FLUSH operation, or WBINVD instruction hits a modi-
fied
line in the data cache, the processor drives a 32-byte burst
write cycle (called a writeback) on the bus. Table 2-2 on page 2-
19 shows the relationships between cache accesses,
writethroughs, and writebacks.
WBIWT and PWT determine the MESI state of a cache line
after a read miss (and resulting cache-line fill) or a write hit.
During read misses, these two signals are interpreted along
with the states of the CACHE output and the KEN input. Dur-
ing write hits, WBIWT and PWT alone determine the resulting
MESI state of a cache line. Tables 5-17 and 5-18 shows the rela-
tionship between WBIWT and PWT for reads (Table 5-17) and
writes (Table 5-18). If WBIWT is Low or PWT is High during a
read miss or write hit, the accessed line is cached in, transi-
tions to, or remains in the shared state after the read or write.
If PWT is Low and WBIWT is High, the accessed line is cached
Ill, transitions to, or remains in the exclusive state after a read
miss or the first write hit to that line. If the line transitions to
Bus Interface