AMD AMD5K86 - Special Bus Cycles

AMD~
18524BjO-Mar1996 AMD5t1J6 Processor Technical Reference Manual
5.4.6 Special Bus Cycles
The processor drives D/C = 0, MIIO = 0, and W!R = 1 to define a
special bus cycle. The values of these cycle-definition signals
are the same for all special cycles. Only BE7-BEU and A31-A3
differentiate among the special cycles, as shown in Table 5-23.
This function of BE7-BEU bears no relationship to the D63-DO
data bus. It is particularly apparent in the case of the branch-
trace message special bus cycle, during which the value of
BE7-BEU is DFh (1101_1111b) but, in contradiction to the byte-
enable bits, the four bytes on D31-DO carry valid data during
both cycles of the operation. During the first cycle, D31-DO
carries the EIP value of the source (branch) instruction. Dur-
ing the second cycle, D31-DO carries the EIP value of the
branch-target instruction.
TABLE 5-23. Encodings For Special Bus Cycles
BE7-BU
A31-A3
Special Bus Cyele
t
Cause
FEh
... OOh Shutdown
Triple fault
FDh ... OOh Cache Invalidation
INVD instruction
FBh ... 10h
Stop Grant STPCr::K
FBh
... OOh Halt
HLT instruction
F7h ... OOh
Cache Writeback and Inval-
WBINVD
instruction
idation
EFh ... OOh Fr::USH Acknowledge Fr::USH
Bit 5 = 1 and bits 3-1 = 001 in the
DFh ... OOh
Branch-Trace Message
2
hardware configuration register
(HWCR). See Section 7.1 on page
7-3 for details.
Notes:
1.
For all special bus cycles, D/C = Q M/fO = 0 and W/R = 1. System logic must retum 7JIW'1 in response to this cycle.
2. The message in a branch-trace message special bus cycle is different in the AMD5t!36 and Pentium processors.
Bus Cycle Timing 5-J8J