AMD AMD5K86 - HITM (Inquire Cycle Hit to Modified Line)

AMD~
18524BjO-Mar1996
AMD5xB6 Processor Technical Reference Manual
TABLE 5-11. MESI-State Transitions for Inquire Cycles
Result of Cache Lookup
Signal or Event Inquire Hit
Inquire Miss
shared or exclusive modified
HIT 1
0 0 0 0
JIITMl 12
1 1 0 0
INV
-
1 0 1 0
Write to Memory
writeback writeback
no no
no
(32 bytes) (32 bytes)
State After Inquire
3
-
invalid shared
invalid
shared
Notes:
-
Don't care or not applicable.
I.
2.
3.
Asserted only for data cache hits to modified lines. Instruction cache lines can only be in the shared or invalid state.
tflT!VI is never asserted while HIT is negated.
Transition occurs after any write to memory. Lines in "shared" MESI state are said to be in "writethrough" state. Those in "exclusive"
or "modified" MESI states are said to be in "writeback" state.
Inquire cycle logic in systems with look-through caches, how-
ever, normally monitor both HIT and HITM because such sys-
tems often implement the write-once cache protocol. The
write-once protocol requires caching in the exclusive state at
certain transitions, and the exclusive state can only be identi-
fied if both HIT and HITM: are monitored. For details on this
protocol, see Section 6.2.6 on page 6-19.
Inquire cycles can be driven while LUCK is asserted, if
AHOLD is used to obtain the bus for the inquire cycle. An
inquire cycle cannot hit a line that is involved in a locked oper-
ation (LUCK asserted). The processor prevents this by always
checking its cache tags prior to a locked operation. If the loca-
tion is cached, it is written back (if necessary) and invalidated
prior to the locked operation.
The Pentium processor does not recognize an inquire cycle hit
on an in-progress cache line fill prior to the first BRDY, and it
will cache that line in the exclusive state if PWT = 0 and WBI
WT = 1. This may cause the line to be cached in the exclusive
state in two separate caches if the system supports other cach-
ing masters. In such cases, the AMD5
K
86 processor asserts HIT
and caches the line in the shared state or does not cache it,
depending on the state of the INV signal.
Signal Descripaons
5-73