AMD AMD5K86 - HITM (Inquire Cycle Hit To Modified Line)

AMD~
AMD5J136 Processor Technical Reference Manual 18524B/O-Mar1996
5.2.26
Summary
Driven
Details
5-74
HI1M (Inquire Cycle Hit To Modified Line)
Output
The processor asserts IIITM to indicate that an inquire cycle
hit a modified line in the processor's data cache. If this occurs,
the processor writes the line back to memory during or after
the bus-hold tenure, depending on which signal is holding the
processor off the bus. HIT is always asserted whenever IIITM
is asserted.
The processor drives IIITM every clock. The signal changes
state two clocks after the assertion of EAUS. If the inquire
cycle misses the cache or hits an exclusive or shared line in the
cache, the processor holds IIITM negated and another inquire
cycle can begin in that clock (two clocks after EAUS). If the
inquire cycle hits a modified line in the data cache, the proces-
sor asserts IIITM and holds it asserted until one clock after the
last BRDY of the write back, then negates it.
IIITM is driven at all times, except while the processor is in the
Stop Clock state, or while RESET or INIT is asserted.
The processor asserts IIITM when an inquire cycle address
matches the address of a modified line in the processor's data
cache. The processor then attempts to drive a four-transfer
burst writeback of the modified line. If INV was asserted at the
time EAUS was asserted for the inquire cycle, a hit leaves the
written-back line in the invalid state. If INV was negated at the
time EADS was asserted, a hit leaves the written-back line in
the shared state. For a comparison of the states that IIITM,
HIT, and INV can assume, see Table 5-11 on page 5-73.
System logic can use HITl\iI to inhibit access to the bus by other
masters (via BUFF or HOLD) until the writeback associated
with the hit has completed. The time at which the write back
occurs depends on which input signal was used to hold the pro-
cessor off the bus for the inquire cycle:
• If AHOLD was used, the processor drives the writeback as
early as two clocks after asserting IIITM, whether or not
AHOLD is still asserted at that time.
• If BUFF or HOLD was used, the processor delays the write-
back until after BUFF or HLDA is negated. In the case of
BUFF, the writeback is driven before any aborted bus cycle
is restarted.
Bus Interface