AMD AMD5K86 - Clock Control; State Transitions; Halt State

AMD~
AMD51J6 Processor Technical Reference Manual
18524B/O-Mar1996
6.4.1
6.4.2
6-14
tions can be entered from any of the processor's normal operat-
ing modes (Real, Virtual-8086, or Protected mode), from
system management mode (SMM), or from the Halt state.
In typical PC systems that implement power control, the STF-
CLK, CLK, and sm signals are driven by external power man-
agement logic that monitors activity on the address and cycle-
definition signals. In a typical case, the power management
logic may notice that, after having initiated SMM to power
down one or more 1/0 devices, another several minutes have
elapsed without activity. Power management logic can again
assert sm, the SMM service routine would obtain the relevant
information and decide to power itself (the processor) down,
and the decision would be communicated to the power man-
agement logic, which would assert sTpcLK to the processor
and, optionally, stop driving CLK to the processor and other
logic. For details on sm and STPCLK, see pages 5-117 and
5-123, respectively.
State Transitions
The five states in the processor's clock-control protocol, as
shown in Figure 6-6, are as follows:
• Normal Execution: Real mode, Virtual-8086 mode, Protected
mode, or System Management Mode (SMM). In this state,
all clocks run at full speed.
• Halt State
• Stop Grant State
• Stop Grant Inquire State
• Stop Clock State
The sections below describe each of the four low-power states.
Halt State
The processor enters the Halt state from the normal operating
modes (Real, Protected, or Virtual-8086) or SMM when it exe-
cutes the HLT instruction. The processor leaves the Halt state
and returns to its prior operating mode when RESET, sm,
INIT, NMI, or INTR is asserted. If STPCLK is asserted within
the Halt state, the processor transitions to the Stop Grant
System Design