AMD AMD5K86 - Page 144

AMD~
1 8524B/O-Marl 996
AMD51J6 Processor Technical Reference Manual
5.1.3 ADS (Address Strobe)
Output
Summary
Driven and Floated
Details
Signal Descriptions
The processor asserts A.DS to specify the beginning of a mem-
ory or 110 bus cycle, or a cache write back to memory. The sig-
nal validates the processor's address and cycle definition
signals and it can be used by system logic to enable accesses to
memory and 110.
During processor-initiated bus cycles, the processor asserts
A.DS for one clock at the beginning of each bus cycle. During
writeback cycles, whether initiated by the processor or by sys-
tem logic, the processor asserts ADS for one clock as early as
two clocks after the processor asserts RITM. The processor can
assert ADS as early as two clocks after the assertion of BRDY
(thus allowing one idle or dead clock between any two bus
cycles), and one clock after the negation of AHOLD, BUFF, or
HLDA.
ADS is driven during memory cycles (including cache
writethroughs and writebacks), 110 cycles, locked cycles, spe-
cial bus cycles, and interrupt acknowledge operations in the
normal operating modes (Real, Protected, and Virtual-8086)
and in SMM, or while PRDY is asserted. While AHOLD is
asserted, and during the Shutdown, Halt, and Stop Grant
states, A.DS is driven only for writebacks that result from
inquire cycle hits. A.DS is not driven during the Stop Clock
state, or while BUFF, HLDA, RESET, or INIT is asserted.
The processor floats A.DS one clock after system logic asserts
BUFF and in the same clock that the processor asserts HLDA.
The processor initiates bus cycles for the purpose of reading
and writing memory or 110, and for writebacks of modified
cache lines. While the processor controls the bus, or while it is
writing back a modified cache line (whether in control of the
bus or not), A.DS defines the beginning of the cycle. In the
clock that it asserts ADS, the processor also begins driving the
several signals that define and qualify the bus cycle, including
A31-A3 (or A31-AS for writebacks), AP, the cycle definition
signals (DR;,MIIU and WIR), BID-BRO, BREQ, ALUM, CACHE,
IDCK, PCD, PWT and SCYC.
If ADS initiates a cache line fill and all four ways of the cache
that could accommodate the incoming line are filled with valid
5-25