AMD AMD5K86 - HOLD (Bus-Hold Request)

AMD~
AMD5~6 Processor Technical Reference Manual 1 8524B/O-Marl 996
5.2.28
Summary
Sampled and
Acknowledged
Details
5-78
HOLD (Bus-Hold Request)
Input
When system logic asserts HOLD, the processor completes any
in-progress bus cycle, floats its cycle-driving outputs, and
asserts HLDA to acknowledge the HOLD.
The processor samples HOLD every clock. It acknowledges
HOLD by floating the cycle-driving outputs on the bus and
asserting HLDA two clocks after the last BRDY of an in-
progress bus cycle, if such a cycle is in progress when HOLD is
asserted, or two clocks after the assertion of HOLD, whichever
comes last. The processor continues to float the bus and assert
HLDA until two clocks after HOLD is negated.
HOLD is sampled during memory cycles (including cache
writethroughs and writebacks), I/O cycles, inquire cycles, and
special bus cycles in the normal operating modes (Real, Pro-
tected, and Virtual-8086) and in SMM; in the Shutdown, Halt,
Stop Grant, and Stop Clock states; or while AHOLD, BUFF,
RESET, INIT, or PRDY is asserted. HOLD is not sampled dur-
ing locked cycles or interrupt acknowledge operations.
The assertion of HOLD, like BUFF but unlike AHOLD, forces
the processor to relinquish the full address and data bus to
another bus master. The signal can be used for the following
purposes:
• Bus Turnaround-Another bus master can assert HOLD to
the processor to obtain control of the bus, allowing the
other bus master to drive any type of bus cycles.
• Inquire Cycles-In multi-master systems with shared mem-
ory, another bus master typically drives an inquire cycle to
the processor or its L2 cache prior to driving a read or write
cycle to any memory locations shared by both masters. Such
inquire cycles can be driven while HOLD is asserted.
HOLD provides the slowest response of the three bus-hold
inputs and is normally useful only in single-bus (non-bridged),
single-processor systems with a look-aside L2 cache. For exam-
ple, a DMA controller may use HOLD to obtain the bus, run
inquire cycles, and perform memory reads and writes. See
Section 6.2.5 on page 14 for system configurations using
HOLD.
Bus Interface