AMD AMD5K86 - HLDA (Bus-Hold Acknowledge)

AMD~
AMD5xB6 Processor Technical Reference Manual
18524B/O-Mar1996
5.2.27
Summary
Driven
Details
5-76
HLDA (Bus-Hold Acknowledge)
Output
When system logic asserts HOLD, the processor completes any
in-progress bus cycle, floats its cycle-driving outputs, and
asserts HLDA as an acknowledgment. While HLDA is asserted,
another bus master can drive cycles on the bus, including
inquire cycles to the processor.
The processor drives HLDA every clock. The processor floats
the cycle-driving outputs on the bus and asserts HLDA two
clocks after the last BRDY of an in-progress bus cycle, if such a
cycle is
in progress when HOLD is asserted, or two clocks after
the assertion of HOLD, whichever comes last. The processor
continues to float the bus and assert HLDA until two clocks
after HOLD is negated.
HLDA is driven during cache hits in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM, but
write backs wait until HLDA is negated. HLDA is also driven in
the Shutdown, Halt, Stop Grant, and Stop Clock states; or
while AHOLD, BUFF, RESET, INIT, or PRDY is asserted.
HLDA is not driven during processor-originated bus cycles,
because any such pending bus cycle completes before the pro-
cessor asserts HLDA.
HLDA is the processor's acknowledgment to HOLD. HLDA
indicates that any in-progress bus cycle has completed and that
the output and bidirectional signals used for memory or 110
accesses are floating. Table 5-12 shows the signals floated. The
same set of signals is floated with BUFF.
TABLE 5-12. Outputs Floated When HLDA is Asserted
Address and Cycle Definition Data and Cache
Address Parity and Control Data Parity Control
A31-A3
DIC
D63-DO CACHE
ADS LUCK
DP7-DPO PCD
:AIJ5C
MIID
nE/-BEU
PWT
AP SCYC
N/A N/A
N/A
W/R
N/A N/A
Bus Interface