AMD AMD5K86 - Page 227

AMD~
AMD5~6 Processor Technical Reference Manual
185248/0- Mar1996
5.2.44
Summary
Samp/edand
Acknowledged
Details
5-108
R/S (Run or Stop)
Input
External hardware and software use RiS to control entry into
and exit from the Hardware Debug Tool (HDT) mode, which
supports access to the processor's DR7-DRO debug registers
through an external debug port. The AMD5
K
86 processor
implements the HDT in a manner different than the Pentium
processor's Probe mode.
The processor samples RiS every clock and recognizes it at the
next instruction boundary. RiS is a level-sensitive interrupt
with an internal pullup resistor. It must be held asserted until
recognized. When recognized, the processor acknowledges R!S
by asserting PRDY at the next instruction boundary.
R!S is sampled during memory cycles (including writethroughs
and writebacks), cache accesses, and 110 cycles in the normal
operating modes (Real, Protected, and Virtual-8086) and in
SMM; in the Shutdown, Halt or Stop Grant states; or while
AHOLD, BUFF, HLDA, RESET, or INIT is asserted. R!S is not
sampled during locked cycles, special bus cycles, or interrupt
acknowledge operations; or during the Stop Clock state.
R!S is the second-highest-priority external interrupt. For
details on its relationship to other interrupts and exceptions,
see Section 5.1.3 on page 5-14 and Table 5-3 on page 5-17.
Test logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
The Hardware Debug Tool (HDT)-sometimes referred to as
the Debug Port or Probe mode-is a collection of signals, regis-
ters, and processor microcode that is enabled when external
debug logic drives RiS Low or loads the processor's Test Access
Port (TAP) instruction register with the USEHDT instruction.
At the next instruction retirement boundary after system
debug logic drives RiS Low or loads the TAP instruction regis-
ter with the USEHDT instruction, the processor performs the
following actions, in the order shown:
1. Flush Pipeline- The processor invalidates all instructions
remaining in the pipeline.
Bus Interface