AMD AMD5K86 - Page 223

AMD~
AMD5x86 Processor Technical Reference Manual
18524B/O-Mar1996
5.2.42
Summary
Driven
Details
5-104
PRDY (Probe Ready)
Output
The processor asserts PRDY to acknowledge the system logic's
assertion of RfS or execution of the Test Access Port (TAP)
instruction, USEHDT, and to indicate the processor's entry
into the Hardware Debug Tool (HDT) mode for debugging.
The processor drives PRDY every clock in response to either
RfS or the TAP instruction, USEHDT. The processor asserts
PRDY at the next instruction boundary after RfS is sampled
Low or when the USEHDT instruction is executed. The latter
causes the processor to assert PRDY without a transition on
RfS. After PRDY is asserted by either means, the processor
negates PRDY on the later of (a) the clearing of the TAP
instruction register, (b) a TAP reset, or (c) after a Low-to-High
transition on RfS.
PRDY is driven in memory cycles (including writethroughs and
writebacks), cache accesses, and lID cycles in the normal oper-
ating modes (Real, Protected, and Virtual-8086) and in SMM;
in the Shutdown, Halt or Stop Grant states; or while AHOLD,
BUFF,
HLDA, or RESET is asserted. PRDY is not driven dur-
ing locked cycles, special bus cycles, or interrupt acknowledge
operations; during the Stop Clock state; or while INIT is
asserted.
The HDT is entered either when external debug logic drives
RfS Low or loads the TAP instruction register with the USE-
HDT instruction. If RfS is used to initiate the HDT, the debug
logic must hold RfS Low throughout the debug session. If the
USEHDT instruction is used to initiate the HDT, the processor
asserts PRDY without a transition on RfS.
The processor negates PRDY and begins fetching instructions
for normal operation one clock after a Low-to-High transition
on RfS, or when the TAP instruction register is cleared, or the
TAP is reset.
Debug software can force the processor into SMM, but the pro-
cessor does not recognize sm or any other interrupts while
PRDY is asserted. If system hardware or software wishes to
assert RESET, it must exit the HDT before asserting RESET.
Bus Interface