AMD AMD5K86 - Page 343

AMD~
AMD5~6 Processor Technical Reference Manual
18524BjO-Mar1996
TABLE 6-2. SMM State-Save Area Map
Offset (hex) Contents
Size (bits)
Type
FFFC CRO
32
read-only
FFF8 CR3
32
read-only
FFF4 EFLAGS
32
read/write
FFFO EIP 32
read/write
FFEC
ED! 32 read/write
FFE8
ESI 32 read/write
FFE4 EBP
32
read/write
FFEO
ESP 32 read/write
FFDC EBX
32
read/write
FFD8
EDX 32
read/write
FFD4 ECX
32
read/write
FFDO EAX
32 read/write
FFCC
DR6 (FFFF _CFF3h) 32
read-only
FFC8 DR7
32
read-only
FFC4 TR
16 (upper 16 reserved) read-only
FFCO LDTR
16 (upper 16 reserved)
read-only
FFBC
GS
16 (upper 16 reserved) read-only
FFB8 FS
16 (upper 16 reserved)
read-only
FFB4 DS
16 (upper 16 reserved) read-only
FFBO
SS
16 (upper 16 reserved)
read-only
FFAC CS
16 (upper 16 reserved) read-only
FFA8 ES
16 (upper 16 reserved) read-only
FFA4 110 Trap Dword 32 (See Section 6.3.6)
read-only
FFAO reserved 32
-
FF9C
110 Trap EIP
32
read-only
FF98 reserved 32
-
FF94 reserved
32
-
FF90 IDTBase 32 read-only
FF8C IDTLimit 16 (upper 16 reserved)
read-only
FF88 GDTBase 32 read-only
FF84 GDTLimit 16 (upper 16 reserved) read-only
Notes:
I. Locations marked UreservedU may change in future processors.
2. Writing locations marked as uread-onV has unpredictable results.
6-26
System Design