AMD AMD5K86 - Page 142

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Signal Descriptions
AMD~
AMD5J!36 Processor Technical Reference Manual
• The EADS input defines the beginning of the inquire cycle
and validates the input address on A31-A5.
• The AP input carries the even parity bit for the A31-A5
address.
• The APCHK output indicates a parity error for the inquire
cycle address on A31-A5.
During such system-initiated inquire cycles, A31-A5 defines
the starting physical address of a 32-byte cache line that is
being snooped in the processor's on-chip instruction and data
caches. The processor interprets the addresses using its physi-
cal address tags, in conjunction with the A2UM input, in paral-
lel with the processor's own cache accesses that use its linear
cache tags.
If an inquire cycle hits a modified line in the processor's data
cache, the processor performs a writeback. During this write-
back, A31-A5 defines a 32-byte starting address in physical
memory. This address is identified by the processor's assertion
of ADS, just as with all other processor-initiated bus cycles,
and the address must be interpreted by system logic in con-
junction with the A2UM input.
The processor does not control the complete bus during a
writeback caused by an inquire cycle; in these cases, AHOLD,
BUFF or HOLD may still be asserted. However, in addition to
writebacks caused by inquire cycle hits, writebacks can also
occur while the processor controls the bus (by processor-initi-
ated cache-line replacements, internal snoops for self-modify-
ing code, or execution of the WBINVD instruction) or by
system-initiated assertion of the FLOSH signal.
If AHOLD is held asserted throughout an inquire cycle and
writeback, system logic must latch the inquire cycle address
when it asserts EADS. This is required so that, if the inquire
cycle hits a modified line (HITM asserted), the processor need
not drive the writeback address when it asserts ADS for the
writeback, which can occur as early as two clocks after the pro-
cessor asserts HITM. Instead, system logic must use its latched
copy of the inquire cycle address for the writeback. By con-
trast, if system logic always negates AHOLD before the write-
back, the processor will drive the writeback address when it
asserts ADS for the writeback, and system logic need not
retain a copy of the inquire cycle address.
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