AMD AMD5K86 - Page 141

AMD~
AMD5xB6 Processor Technical Reference Manual
18524BjO-Mar1996
5-22
addresses on A31-A3. In this manner, BID-REO replace the
function of address bits A2-AO, which do not exist.
When the processor drives burst reads it drives the starting
address on A31-A3 (which is the address of the quadword that
contains the instruction or data required) and it drives BE7-
BEO to specify the required bytes in that quadword. (This
addressing method is unlike the 486 processor, which drives
separate addresses for each transfer of a burst.) System logic
must determine the remaining three quadword addresses as
shown in Table 5-4.
When the processor drives burst writes (writebacks), it drives
the starting address on A31-A3 in the same manner as for
burst reads, but it enables all eight bytes (BE7-BEO = OOh)
because it always starts writebacks at 32-byte aligned
addresses (address of the first quadword is xxxx_xxOOh). Thus,
A4-A3 are always OOb for writebacks.
TABLE 5-4. Address-Generation Sequence During Bursts
Address Driven By
Address of Subsequent Quadwords
1
Processor on A31-A3
Generated By System Logic
Quadword 1 Quadword 2 Quadword 3 Quadword4
... OOh ... 08h
... IOh ... 18h
... 08h
... OOh ... 18h ... IOh
... IOh
... 18h ... OOh ... 08h
... 18h ... IOh ... 08h ... OOh
Notes:
1. quadword = 8 bytes
System logic can derive memory and I/O port select signals, as
well as memory row and address signals, from A31-A3 and the
cycle definition signals. Although the processor does not inter-
pret the A4-A3 signals as part of an inquire cycle address, sys-
tem logic must drive them at valid logic levels (0 or 1) during
inquire cycles, qnd the processor drives both bits to 0 during
writebacks.
While system logic has obtained control of the address bus via
assertion of AHOLD, BUFF or HOLD, the A31-A5 signals
become inputs and define a 32-byte, cache-line, inquire cycle
address in conjunction with the following signals:
Bus Interface