AMD AMD5K86 - Page 213

AMD~
AMD5t1J6 Processor Technical Reference Manual 18524B/O-Mar1996
5-94
The processor always negates mcK for at least one idle clock
between sequential locked operations. For example, if a read-
modify-write is followed by another read-modify-write, there is
an unlocked idle clock (sometimes called a dead clock)
between the two sequences to allow system logic to reallocate
the bus to another bus master. During this idle clock, the pro-
cessor responds to all signals and pending interrupts.
The processor responds to AHOLD and BUFF while mcK is
asserted, and it recognizes but does not respond to HOLD until
the clock after the last BRDY of the locked operation. The pro-
cessor recognizes all other inputs and outputs used for memory
cycles except KEN, NA, and WBIWT.
Inquire cycles can be driven while·mcK is asserted if AHOLD
is used to obtain the bus for the inquire cycle. If such an
inquire cycle occurs before the last write of the locked opera-
tion and the inquire hits a modified cache location, the write-
back is done in the middle of the locked operation between the
two locked cycles with mcK asserted during the writeback.
System logic must recognize this case and know that the
inquire cycle is snooping and writing back a different location
than the one that is locked.
Locked operations cannot be performed on cached locations,
and an inquire cycle cannot hit a line that is involved in the
locked operation. The processor prevents this by always check-
ing its cache tags prior to a locked operation. If the location is
cached, it is written back (if necessary) and invalidated prior
to the locked operation. This policy is necessary to support reli-
able semaphores for multiple caching devices, because such
semaphores must never be cached and should only be accessed
using locked operations.
If system logic asserts AHOLD while the processor is complet-
ing a locked cycle already begun before the assertion of
AHOLD, the system must not allow accesses by other bus mas-
ters to lock the same address that the processor is locking.
If BUFF is asserted during a locked operation, only the cycle(s)
aborted before their last BR1JY and the cycles not yet run are
restarted after BUFF is negated. Thus, system logic must keep
track of all cycles in the locked operation that have completed
before the assertion of BUFF and must continue the locked
operation immediately after BUFF is negated, except that if a
Bus Interface