1 8524B/O-Marl
996
Signal
Descriptions
AMD~
AMD5~6
Processor
Technical
Reference
Manual
four-byte
write
sequence.
The
Pentium
processor,
however,
drives
a
locked
eight-byte
read
and
one-byte
write
sequence.
Independent
of
these
actions
by
the
processor,
the
operat-
ing
system
can
clear
the
Accessed
or
Busy
bits
to
0
for
book-
keeping
purposes.
The
operating
system
may
do
this
however
it
wishes,
but
if
locking
is
to
be
used
for
the
mem-
ory
accesses
it
is
the
operating
system's
responsibility
to
initiate
locking
with
an
XCHG
or
a LOCK
instruction
pre-
fix.
• Page Directory
and
Page Table
Accesses-The
processor
per-
forms
these
accesses
during
each
TLB
miss
to
set
the
Accessed
(A)
bit
to
1
in
the
relevant
page
directory
and/or
page
table
entry,
and
during
each
write
access
to
set
the
Dirty
(D)
bit
to
1
in
the
relevant
page
table
entry,
if
those
bits
are
not
already
set.
These
accesses
work
in
a
manner
similar
to
descriptor
table
accesses,
described
immediately
above,
except
that
the
operating
system
typically
clears
the
Accessed
and
Dirty
bits
before
the
processor
sets
them,
so
that
the
operating
system
can
thereafter
identify
pages
that
have
been
accessed
and
updated.
• XCHG
Instruction-When
XCHG
is
used
to
swap
a
register
with
a
memory
location,
the
access
is
unconditionally
locked.
•
LOCK
Prefix-Applications
programs
can
add
the
LOCK
prefix
to
the
following
instructions
if
the
destination
oper-
and
resides
in
memory:
ADC, ADD, AND, BT, BTC, BTR,
BTS, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR,
and
XCHG
(redundant).
The
locking
applies
only
to
the
bus
cycle
gen-
erated
by
that
single
instruction.
Other
uses
of
the
LOCK
prefix
generate
an
undefined
opcode
fault.
Locked
operations
normally
consist
of
pairs
of
bus
cycles, typi-
cally
read
followed
by
write,
except
in
the
case
of
interrupt
acknowledge
pairs
which
are
read-read.
If
the
locked
cycles
are
misaligned,
the
processor
runs
multiple
pairs
of
bus
cycles,
during
which
'LUCK
and
SCYC
are
both
asserted
throughout.
For
example,
a
misaligned,
locked,
read-modify-write
sequence
appears
on
the
bus
as
two
read
cycles
followed
by
two
write
cycles.
Thus,
up
to
four
bus
cycles
can
occur
for
misaligned
accesses.
(The
AMD5
K
86
processor
runs
certain
misaligned
bus
cycles
in
the
opposite
order
from
the
Pentium
processor;
see
the
description
of SCYC
on
page
5-115
for
details.)
5-93
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