AMD AMD5K86 - LOCK (Bus Lock)

AMD~
AMD5J!J6 Processor Technical Reference Manual 18524BjO-Mar1996
5.2.35
Summary
lOCK (Bus Lock)
Output
The processor asserts :r::ucr during certain sequences of bus
cycles that require integrity. To preserve the processor's han-
dling of these sequences, system logic should prevent other
bus masters from intervening in locked cycles.
Driven and Floated
For locked operations, the processor asserts mcK with ADS
and holds it asserted until the last expected BRDY of the last
bus cycle in the locked operation. The processor negates mcK
for at least one clock (called a dead or idle clock) between
sequential locked operations.
Details
5-92
mcK is driven during memory cycles and interrupt acknowl-
edge operations in the normal operating modes (Real, Pro-
tected, and Virtual-8086) and in SMM. LOCK is not driven or
not meaningful during cache writethroughs or writebacks, I/O
cycles, or special bus cycles; in the Shutdown, Halt, Stop Grant,
or Stop Clock states; or while BOFF, HLDA, RESET, INIT, or
PRDY is asserted. While AHOLD is asserted, LOCK is driven
only to complete a locked cycle that had been initiated before
AHOLD was asserted.
The processor floats mcK one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
The processor always locks the following types of memory
operations:
• Interrupt Acknowledge Operations-These are a pair of read
cycles used to obtain an interrupt vector in response to the
assertion of INTR.
• Descriptor-Table Accesses-These involve segment descrip-
tors in the global descriptor table (GDT), local descriptor
table (LDT) or interrupt descriptor table (IDT) and occur in
Protected mode. The processor performs them during a seg-
ment load to ensure that the Accessed (A) bit in code and
data descriptors is set to 1, or to test and set the Busy (B) bit
in TSS descriptors. The sequence is as follows: (1) the pro-
cessor drives an unlocked read of the descriptor to see if
the relevant bit is set to 1, (2) if the bit is cleared to 0, the
processor then drives a locked read-modify-write to set the
bit to 1. During updates to the Accessed and Busy bits, the
AMD5
K
86 processor drives a locked four-byte read and
Buslnterface