AMD AMD5K86 - Page 125

AMD~
AMD5,!36 Processor Technical Reference Manual
18524B/O-Mar1996
TABLE 5-1. Summary of Signal Characteristics (continued)
Signal Type
Sampled (Input) or
Internal
Floated
3
Asserted (Output)2 Resistor
From two clocks after last :BRDY of an in-
HLDA
0
progress bus cycle, or two clocks after
HOLD, whichever comes last, until two
clocks
after HOLD is negated.
HOLD I Every clock. Acknowledged with HLDA.
!ERR 0
Every clock, in the Functional-Redundancy
Checking mode.
IGNNEl
I
Every clock.
INITl
I
Every clock. Rising-edge-triggered. Recog-
nized at next instruction boundary.
Every clock. Level-sensitive. Recognized at
INTRl
I
next instruction boundary. Acknowledged
with an interrupt acknowledge operation.
INV I EveryEAD"S.
First :BRDY or NA of bus cycle, whichever
KEN I
comes first. Recognized only during read
cycles.
From ADS until last expected BRDY of the
r:ucK 0
bus cycle. Negated for one clock (dead BOFF +1 or
cycle) between sequential locked opera- HLDA
tions.
MJID 0
From ADS until last expected BRDY of the BOFF +1 or
bus cycle. HLDA
From one clock after ADS until the first
NA I
expected BRDY of a bus cycle. The only
function of NA is to validate KEN or WBI
WT in place of BRDY.
NMIl
I
Every clock. Rising-edge-triggered. Recog-
nized at next instruction boundary.
PCD 0
From ADS until last expected BRDY of the BOFF +1 or
bus cycle. HLDA
PCHK 0
Two clocks after every BRDY of read cycles.
PEN I
Every :BRDY of read cycles, and second
BRDY of interrupt acknowledge operation.
Notes:
1.
Can be driven asynchronously or synchronously.
2. The term clock means bus clock (CLK). "+n" means n CLKs later.
3. "+n" means n CLKs after the named signal is sampled active. All outputs and bidirectionals are floated during the float test (FITJSR
at RESET).
5-6
Bus Interface