AMD AMD5K86 - Page 124

AMD~
18524B/O-Mar1996
AMD5;J6 Processor Technical Reference Manual
TABLE 5-1. Summary of Signal Characteristics (continued)
Signal
Type
Sampled (Input) or
Internal
Floated
3
Asserted (Output)2
Resistor
CLK I
Always.
Drc 0
From ADS until the last expected "BRDY of BUFF +1 or
the bus cycle. HLDA
Output (single transfer): From one clock
after AIJS"" until BRDY.
Output (burst transfer): From one clock after
BUFF +1 or
D63-DO 1/0
ADS until the first"BRDY, and thereafter
HLDA
from one clock after each "BRDY until the
next"BRDY.
Input: Every BRDY.
DP7-DPO
110
(same as D63-DO)
BUFF +1 or
HLDA
Every clock while AHOLD, BUFF or HLDA
is asserted, beginning two clocks after the
assertion of AHOLD, two clocks after the
EAUS
I
assertion of BUFF, or one clock after the
assertion of HLDA; except while the proces-
sor drives A31-A3, while it asserts HITl\l,
and one clock after EAUS.
With"BRDY
of external write cycles and in
EWBE
I
every clock thereafter until EWBE is
asserted.
FERR 0
Every clock.
Every clock. Falling-edge-triggered. Recog-
nized at next instruction boundary.
FLuSHl I
Acknowledged with Flush-Acknowledge spe-
cial bus cycle.
FRCMCl I
Every clock in which RESET is asserted.
Every clock. Changes state two clocks after
HIT
0
EAUS and retains that state until two clocks
after next EAUS.
Every clock. Changes state two clocks after
HITl\l 0
EAUS and retains that state until one clock
after the last BRDY of writeback.
Notes:
I. Can be driven asynchronously or synchronously.
2.
The term clock means bus clock (CLK). "+n" means n CLKs later.
3.
"+n" means n CLKs after the named signal is sampled active. All outputs and bidirectionals are floated during the float test (FT1JSR
at RESET).
Signal Overview 5-5