AMD AMD5K86 - Page 123

AMD~
AMD5xB6 Processor Technical Reference Manual
18524B/O-Mar1996
5.1.1 Signal Characteristics
TABLE 5-1. Summary of Signal Characteristics
Signal Type
Sampled (Input) or
Internal
Floated
3
Asserted (Output)2 Resistor
~1
I
Every clock.
Output: From ADS until last expected
AHOLD +1,
BRDY of the bus cycle.
A31-A3
110
B1JFF +1 or
Input: Same clock as EADS. A4-A3 are dis-
HLDA
abled for input.
ADS 0 First clock of bus cycle.
B1JFF +1 or
HLDA
AUSC
0 First clock of bus cycle.
B1JFF +1 or
HLDA
AHOLD I
Every clock.
AHOLD +1,
AP
110
(same as A31-A3)
B1JFF +1 or
HLDA
APCHK 0 Two clocks after EADS, for one clock.
BE7-BEU 0
From ADS until the last expected BRDY of
B1JFF +1 or
the bus cycle. HLDA
BF I
Falling edge of RESET. pullup
BUFF I
Every clock.
BRDY I
Every clock, from one clock after ADS until
the last expected BRDY of the bus cycle.
BRDYC I (same as BRDY) pullup
First clock of every bus cycle (same as
ADS), cache store, cache-tag recovery, and
BREQ
0
aliased cache load. Asserted continuously
while processor is held off bus and needs
access to continue.
BUSCHK
Every BRDY. Recognized at the next
I
instruction boundary.
pullup
From ADS until the last expected BRDY of
B1JFF +1 or
CACHE 0 the bus cycle. Driven for all reads; only
HLDA
driven for writes during writebacks.
Notes:
1. Can be driven asynchronously or synchronously.
2. The term clock means bus clock (CLK). "+nH means n CLKs later.
3.
"+n" means n CLKs after the named signal is sampled active. All outputs and bidirectionals are floated during the float test (F[[JSR
at RESET).
5-4
Bus Interface