AMD AMD5K86 - Page 162

18524BjO- Mar1996
Signal Descriptions
AMD~
AMD5J116 Processor Technical Reference Manual
The processor samples BRDY during all types of bus cycles,
including the following:
• Single-transfer reads
• Single-transfer writes (including cache writethroughs)
• Burst reads (cache line fills)
• Burst write backs
• Special bus cycles
• Interrupt acknowledge cycles
The number of BRDY s expected by the processor depends on
the type of bus cycle, as follows:
• One BRDY for an aligned single-transfer cycle, a special
bus cycle, or each of two cycles in an interrupt acknowledge
operation. Additional BRDY s are needed for misaligned
cycles.
• Four BRDY s, one for each data transfer in a burst cycle.
BRDY may be held asserted throughout the four transfers
of the burst.
All data transfers that are not performed as bursts are per-
formed as one or more single-transfer cycles. For write cycles,
EWBE must be asserted either with or after BRDY in order for
any further writes or certain other operations to be performed
(see the description of EWBE on page 5-63). If system logic
returns more BRDY s than the processor expects for a single-
transfer cycle or a burst cycle, the processor ignores them.
The processor samples the following inputs in the clock in
which system logic asserts BRDY:
•
D63-DO-Every BRDY, for all bus cycles.
• DP7-DPO-Every BRDY, for all bus cycles.
• BUSCHK-Every BRDY, for all bus cycles.
• EWBE-Every BRDY, for write cycles.
• KEN - First BRDY or NA, whichever occurs first, for read
cycles.
• PEN - Every BRDY for read cycles, and second BRDY of
interrupt acknowledge operations.
• WBIWT - First BRDY or NA, whichever occurs first, for
read and write cycles.
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