AMD AMD5K86 - Page 161

AMD~
AMDSIJ6 Processor Technical Reference Manual
18524B/O-Marl996
5.2.11
Summary
Sampled
Details
5-42
BRDY (Burst Ready)
Input
For bus cycles that transfer data, system logic must assert
BRDY to indicate that it has received a data transfer on D63-
DO during a write and to indicate that it has placed valid data
on D63-DO during a read. Up to eight bytes of data-the width
of the D63-DO data bus-are validated with each BRDY. For
special bus cycles, system logic must assert BRDY either to val-
idate data or as a simple handshake.
The processor samples BRDY every clock, from one clock after
ADS until the last expected BRDY of the bus cycle.
BRDY is sampled during memory cycles (including cache
writethroughs and writebacks), 110 cycles, locked cycles, spe-
cial bus cycles, and interrupt acknowledge operations in the
normal operating modes (Real, Protected, and Virtual-8086)
and in SMM, or while PRDY is asserted. While AHOLD is
asserted, BRDY is sampled only to complete a bus cycle that
had been initiated before AHOLD was asserted, or for inquire
cycle writebacks. During the Shutdown, Halt, and Stop Grant
states, BRDY is sampled only for inquire cycle writebacks.
BRDY is not sampled when the processor is not driving an
external bus cycle; or during the Stop Clock state; or while
BOFF, HLDA, RESET, or INIT is asserted.
If BRDY is asserted simultaneously with BOFF, BOFF is recog-
nized and BRDY is not, but if BRDY is asserted simultaneously
with HOLD, BRDY is recognized and the HOLD waits until the
bus cycle associated with the BRDY completes.
BRDY is associated with a transfer of one to eight bytes on the
D63-DO data bus. During memory and I/O reads, the processor
samples and latches the bytes on D63-DO and the parity bits on
DP7-DPO that are enabled by BE7-BEU when system logic
asserts BRDY. During memory and I/O writes, the processor
waits for system logic to return BRDY before transferring
more data on D63-DO or before starting another bus cycle.
Delays in returning the BRDY for a transfer (and delays in
returning EWBE for a write cycle) are said to add wait states to
the transfer, although these states are nothing more than the
absence of an expected BRDY.
Bus Interface